1. Field of the Invention
The present invention relates to a memory cell of a semiconductor device, and more particularly, to a Static Random Access Memory (SRAM) cell having a bit line shorter than a word line.
2. Description of the Related Art
An SRAM device requires no refresh operation and has a higher operation speed than a Dynamic Random Access Memory (DRAM) device, and low power consumption. Thus, the SRAM device is widely used for a cache memory of a computer or portable electronic device. A unit cell of the SRAM device is composed of a pair of driver transistors, a pair of transfer transistors and a pair of load devices. An SRAM cell may be either a high load resistor cell or a CMOS type cell, depending on a load device type. The high load resistor cell uses a high load resistor of approximately 1.times.10.sup.9 .OMEGA. or more as the load device, and is stacked on the driver transistor and the transfer transistor which are NMOS transistors. In the CMOS type cell, both the driver transistor and the transfer transistor are NMOS transistors, and the load device is a PMOS transistor. The PMOS transistor used for the load device is a thin film transistor (TFT) or a bulk transistor. If the PMOS transistor used for the load device is a bulk transistor, the cell area is increased. However, if a TFT is used for the load device, the TFT can be stacked on the driver transistor and the transfer transistor. Thus, in the SRAM cell in which the TFT is used as the load device, the cell area can be minimized similar to a high load resistor cell.
As described above, since the SRAM cell using the TFT or resistor as the load device can minimize the cell area, it is widely used for a highly-integrated SRAM device.
FIG. 1 is a layout diagram of an SRAM cell disclosed in U.S. Pat. No. 5,379,251.
Referring to FIG. 1, an isolation area 24 defining a pair of active areas which are parallel with each other along the y-direction, is arranged on a semiconductor substrate. In each of the active areas, a transfer transistor and a driver transistor are arranged in series. Also, a pair of transfer transistors formed on active areas adjacent to each other shares a gate electrode passing the center of the cell and intersecting the active area, i.e., a word line 21. The word line 21 and the gate electrodes 22 and 23 of the driver transistor are not concurrently formed in the process. A node contact 25 is arranged between the driver transistor and the transfer transistor connected in series with the driver transistor, and a gate electrode contact 27 is arranged on the gate electrodes 22 and 23, of each of the driver transistors. Thus, two node contacts 25 and two gate electrode contacts 27 are formed in a cell. The active area exposed by the node contact 25 is connected to the gate electrode of the driver transistor which is adjacent to the exposed active area along the y-direction through the gate electrode contact 27, to form a latch circuit. Also, a ground contact 28 is arranged on a source area of each of the driver transistors, and a bit line contact 26 is arranged on a drain area (or a source area) of each of the transfer transistors. Although it is not shown in FIG. 1, in the U.S. Pat. No. 5,379,251, it is disclosed that a ground plate exposing the upper portion of the bit line contact 26 and covering the ground contact 28 is arranged on the entire surface of the cell area.
In the SRAM cell disclosed U.S. Pat. No. 5,379,251, the length of the cell in the y-direction is longer than in the x-direction. Thus, the bit line is longer than the word line in one cell. As the bit line is longer, parasitic capacitance of the bit line is more, thereby increasing the delay time of a signal transferred through the bit line. As a result, it is difficult to improve the operation speed of the SRAM device. Also, according to the SRAM cell disclosed U.S. Pat. No. 5,379,251, there is a portion in which the word line overlaps the gate electrode of the driver transistor. That is, the word line, acting as the gate electrode of the transfer transistor, and the gate electrode of the driver transistor are not formed in the same process. Thus, the manufacturing process of the SRAM cell is complicated, and the parasitic capacitance of the word line is increased, so that it is difficult to rapidly select a desired cell. Meanwhile, as disclosed in the U.S. Pat. No. 5,379,251, the ground plate covering all of the ground contact is arranged on the entire surface of the cell array area, to thereby minimize voltage drop caused by the ground plate, which can improve an operating voltage margin of each cell. However, this also increases the parasitic capacitance between the bit line and the ground plate and the parasitic capacitance between the word line and the ground plate, which makes the operation speed of the SRAM device slow.
FIG. 2 is an equivalent circuit diagram of a part of the cell array area in which other conventional SRAM cells, unlike that of FIG. 1, are arranged in a matrix.
Referring to FIG. 2, a plurality of SRAM cells C11, C12, . . . , C1n, . . . are connected to the first word line WL1, running in the x-direction, and share a first ground line V.sub.ss1. A plurality of SRAM cells C21, C22, . . . , C2n, . . . are connected to a second word line WL2, running parallel to the first word line WL1, and share a second ground line V.sub.ss2. That is, the ground lines and the word lines run in the x-direction. Also, a power supply line V.sub.cc which supplies power to each cell is arranged parallel to the word lines.
Meanwhile, the cells C11, C21, . . . , running in the y-direction of FIG. 2, share a pair of bit lines BL1 and /BL1. Also, the cells C12, C22, . . . share another pair of bit lines BL2 and /BL2. Thus, the word lines intersect the bit lines.
As shown in FIG. 2, the SRAM device in which a plurality of cells connected to a word line share one ground line has a reduced operation voltage range of its SRAM cells. For example, if a power voltage V.sub.cc is applied to the first word line WL1 in order to select one cell from the cells C11, C12, . . . , C1n, . . . connected to the first word line WL1, transfer transistors of all cells connected to the first word line WL1 are turned on. Accordingly, cell currents /.sub.1, /.sub.2, . . . , /.sub.n, . . . flow through all cells C11, C12, . . . , C1n, . . . from bit lines BL1, /BL1, BL2, /BL2, . . . , BLn, /BLn, . . . precharged to a predetermined voltage, e.g., a power supply voltage. At this time, the voltage drop caused by the cell currents /.sub.1, /.sub.2, . . . , /.sub.n, . . . occurs in the first ground line V.sub.ss1. The voltage drop is caused by resistance Rs of the ground line and contact resistance Rc between a source area of the driver transistor and the ground line. As a result, the current which flows through all cells C11, C12, . . . , C1n, . . . connected to the first word line WL1 flows through a ground line, i.e., the first ground line, so that a positive (+) voltage higher than the ground voltage is induced to the source area of the driver transistor of each cell. Accordingly, the highest positive voltage is induced to the source area of the driver transistors of cells C1n and C2n further from an end the word line. For example, if the power supply voltage V.sub.cc is applied to the first word line WL1, cell currents /.sub.1, /.sub.2, . . . , /.sub.n, . . . flow through the first ground line Vss1 from all cells C.sub.11, C.sub.12 . . . , C.sub.1n, . . . connected to the first word line WL1. At this time, the voltage V.sub.SN induced to the source area of driver transistors of the nth cell C1n is as follows: ##EQU1##
It is understood in Formula 1 that as more cells share a ground line, the voltage induced to the source area of the driver transistor of the cell farthest from the end of the ground line is higher. Thus, the operation voltage range of the SRAM cell is reduced, to thereby deteriorate the low voltage characteristics of the SRAM device.